S12 Clock
Since your application, most likely, will be designed to run upon power up of the module without the support of the serial monitor, it will need to configure the clock registers on the 9S12G hardware. The reason for this is that if the Load/Run switch is in the Run position, the serial monitor detects this setting upon powerup or reset and jumps immediately to your application as pointed to by the address you put in Flash at $F7FE/F. (If you do not program this location, the serial monitor will take control regardless of the Load/Run switch position!)
When the serial monitor starts your application following reset, it does not configure any of the hardware registers first. It goes directly to your code.
After reset, MCU clock is in PEI mode (refer to 10.1.2 in S12G Manual), so Bus Clock (MCLK) is 6.25 MHz. This means the oscillator based upon the external crystal is not enabled, and the bus clock is generated from the internal 1MHz oscillator, boosted by the PLL to 25MHz and divided by four, resulting in an MCLK frequency of 6.25 MHz.
How is the clock set then to the speed you want? To do that, the hardware uses the following equations:
PLLClock = 2 * Oscillator * (SYNR + 1 ) / (REFDV + 1)
BusClock = PLLCock / 2
The BusClock frequency is the one we want. The Oscillator term is the frequency of the crystal oscillator attached to the chip, or the frequency being fed into the MCU on the EXTAL pin. EsduinoXtreme has an 8 MHz crystal, so this will be the oscillator value. The registers SYNR and REFDV will need to be initialized to get the system clock at the desired value.
Example taken from the Serial Monitor code (S12SerMon2r7):
SYNR: equ CRGV4+$00 ;CRG synthesizer register
REFDV: equ CRGV4+$01 ;CRG reference divider register
POSTDIV: equ CRGV4+$02 ;CRG post divider
CRGFLG: equ CRGV4+$03 ;CRG flags register
LOCK: equ %00001000 ;lock status bit
UPOSC: equ %00000001 ;Oscillator Status Bit
CLKSEL: equ CRGV4+$05 ;CRG clock select register
PLLSEL: equ %10000000 ;PLL select bit
PLLCTL: equ CRGV4+$06 ;CRG PLL control register
PLLON: equ %01000000 ;phase lock loop on bit
CPMUOSC: equ $02FA ;S12CPMU Oscillator Register
OscFreq: equ 8000 ;Osc speed (i.e. external crystal frequency)
initSYNR: equ $02 ; mult by synr + 1 = 3 (24MHz)
VCOFRQ: equ $40 ; vco gain
initREFDV: equ $00
REFFRQ: equ $80 ;pll stability
initPOSTDIV: equ $00 ;Post Divider Register (CPMUPOSTDIV)
movb #initSYNR+VCOFRQ,SYNR ;set PLL multiplier
movb #initREFDV+REFFRQ,REFDV ;set PLL divider
movb #initPOSTDIV,POSTDIV ;set post-divider
movb #$C0,CPMUOSC ;Enable external oscillator
nop
nop
brclr CRGFLG,LOCK,*+0 ;while (!(crg.crgflg.bit.lock==1))
bset CLKSEL,PLLSEL ;engage PLL to system
Clock Usage
The oscillator and bus clocks are used not just to sequence through instructions and time memory and peripheral accesses. They are also used to dictate the timing of several other harware module capabilities, such as SCI baud rate, RTI/COP timing, and Flash/EEPROM programming.
For example, the baud rate for any of the SCI interfaces is set by this equation:
baudRegister = ( (BusFreq / 16) * 10) / baudrate
Here the BusFreq is the system bus frequency as determined above, in KHz. This will usually be 24000 KHz. The baudrate value is the desired baud divided by 100. So 9600 becomes 96, etc. The resulting baudRegister value is then programmed into the SCIBDH and SCIBDL registers as the high and low bytes of the value, respectively.
Obviously, if the system bus clock is changed to a different value, then this will affect the baud rate programmed into the SCI module.
Example coming soon...
