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Using Your Adapt9S12XDP Microcontroller Module - Software Considerations - Memory Map

Article Index
Using Your Adapt9S12XDP Microcontroller Module
Overview of features
Getting Started
Setting Up the Hardware
Application Programming
Software Debugging
Software Considerations
Software Considerations - Memory Map
Software Considerations - Interrupts
Software Considerations - XGATE
Software Considerations - S12X Clock
Hardware Details
All Pages

Memory Map

PPAGE, GPAGE, EPAGE, RPAGE, Direct Page, banking-- and the list goes on, of terms thrown at you relating to addressing memory on the S12X.  It can get confusing trying to figure out how to use all the memory resources available to the new S12X user.  This explanation is written to help clear up the fog.

For your information, the following registers are located in the CPU Address space at these locations:

GPAGE = $0010
PPAGE = $0030
RPAGE = $0016
EPAGE = $0017
DIRECT = $0011

Let's start with the CPU (Central Processing Unit).  This is the processor that handles the actual machine code instructions.  It is designed with 16-bit registers, such as X, Y, and PC (Program Counter).  As such, it can address some 65,536 bytes directly (64K), and not one byte more nor less.  It does not care what is on the other end of an address, be it a register, RAM, Flash, or a penguin dancing on a keypad.  An address is just a place to read or write an 8 bit byte.  Every piece of hardware that the CPU communicates with has to map somewhere into this address space.  We will refer to the CPU address space as the Logical Address.  (It makes logical sense to the CPU to find stuff here!)

One consideration to keep in mind regarding memory accesses is that the CPU is designed as a 16-bit processor.  As such, its accesses are optimized when it is doing fetches and writes to even addresses.  (An even address has a zero in the Least Significant Bit position.)  If the CPU has to do a word access with an odd address, then it actually has to make two accesses, and then manipulate the results to produce the expected results.  This increases latency.  So be sure to remember this when setting up tables that will be read frequently.  (Instruction fetches have this issue mostly alleviated by the use of an instruction queue.)

Since addresses are expressed in 16 bits, it takes two bytes to specify any address.  It takes time to fetch these two bytes that specify an address when the CPU is executing instructions.  However there is a shortcut available to the CPU, and this is where the Direct Page register comes in.  The Direct Page register is at $11 in the CPU Logical Address Space.  The value written here becomes the high order byte used in address accesses for instructions using Direct addressing.  This means that when Direct addressing is done, only one byte is needed to specify the target address in the instruction.  That saves both time and memory usage.

On the S12X the Direct page register is generally a write-once register (after powerup), so you have to choose carefully the value written here.  A good strategy would be to set it up so that it references one of the pages in RAM.  Frequently referenced variables can then be placed in that page.  The resulting code will take less space and run faster.

There are the various memory resources that have been included on the S12XDP512 chip. The Flash consists of 512K of memory.  Physically, the Flash memory would have its memory cells addressed from $00000 to $3FFFF.  This physical address for Flash is never used by the S12X directly, though.  The only time you really need to be aware of it is if you are preparing an S-record file that will be used by Freescale to create a ROM version of the S12X for OEM use.

Notice that the address space for Flash requires 20 bits to specify, not 16 bits.  Obviously, there is an issue here, as the CPU can't directly access this much memory.  Furthermore, Flash is not the only memory-mapped device we want the CPU to access.  There are also:  RAM, EEPROM, and various I/O (Input/Output) devices, such as that dancing penguin.

What Freescale did to solve this problem was to divide up the CPU logical space into sections, each dedicated to its specific device.  We'll get back to this in a moment.

The next step was to devise a way to determine the value of the extra address lines each piece of hardware had.  To do that there had to be a way of tying all this hardware (such as Flash and RAM), together physically so that the CPU could address them.  The  solution was to define something call the Global address space.  Global addresses start at $000000 and go to $7FFFFF and are the physical address space used to reach real hardware, like Flash or RAM.  It takes 23 bits to define this address space, providing room for 8 Megabytes of stuff.  With this much addressing range, that 512K block of Flash can fit in just fine.  Furthermore, room is reserved for larger Flash devices as well.  In fact, with a 144-pin S12X, the full set of address lines is physically available on the device so that other external devices can be addressed by the hardware, as desired by the user.


The internal devices of the S12X were then placed in the Global Address space at fixed locations.  Notice that Flash is at the top of this address space, and here is where things like PPAGE fit in.  To be able to specify the extra address bits which the CPU can't access, registers were defined to accommodate the values for the additional address lines.  PPAGE is for specifically for Flash, RPAGE for RAM, and EPAGE for EEPROM.  The GPAGE register is used to access any of these devices, or any other external devices.

Let's start with GPAGE.  This register is used to define the upper seven address line bits in the 23-bit Global Address space, from bit 16 through bit 22.  (The 16 bits of the CPU Logical Address space go from bit 0 to bit 15.)   The Most Significant Bit of the GPAGE register is always zero, since there is no bit 23 in the Global Address space.  Writing to this register determines the 64K window in the Global Address space that will be accessed by Global read and write instructions.  These include instructions like GLDAA and GLDX.  For our 512K Flash, the GPAGE register will need to have values between $78 to $7F written to it to be able to read the relevant portion of Flash.  Since there is plenty of free space in the Global Address space, other external devices can be added and Global addressing used to access those devices.

GPAGE   PPAGEs referenced
-----   -------
$78     $E0-$E3
$79     $E4-$E7
$7A     $E8-$EB
$7B     $EC-$EF
$7C     $F0-$F3
$7D     $F4-$F7
$7E     $F8-$FB
$7F     $FC-$FF

Note, however, that we can't run code using Global Addressing.  Code can only be run in the Logical Address space of the CPU.  To allow Flash, for example, to be able to run code routines stored in it, it has to be mapped into the Logical Address space of the CPU directly.  This is done by dividing up the Flash into pages of 16K each.  Two of these pages are then fixed into the CPU Logical Address space.  They are always there.  (Okay there are lots of caveats and exceptions I could be going into here, but I'm not going that far for now.)  This way code can be placed in these fixed pages so the CPU has something to tell it what to do when power is first applied.  This is why the interrupt table is in Flash by default.  Space is also allocated in the Logical Address space for a third 16K Flash page.  The hardware Flash page appearing here, though, is determined by the value of the PPAGE register.

For a 512K Flash, the 16K pages are numbered starting at $E0 and going to $FF.  One would think that numbering them should start at $00 and go to $1F, but such is not the case.  This partially has to do with where the Flash is in the Global Address space, namely at the top.  As the possibility exists for larger versions of Flash to become available over time, the space taken by Flash will grow downward.  With 256 pages of 16k bytes each, the maximum possible Flash that can be used by the S12X is 4 megabytes.  If that full amount were available, then the page numbering would go from $00 to $FF.  (With external addressing, a designer could add their own additional memory in this space externally, and then use the PPAGE register to access it.)

The default mapping of Flash to CPU Logical Address space on powerup is as follows:
Flash Bank $FD - CPU Address range is $4000 to $7FFF  (Fixed)
Flash Bank $FE - CPU Address range is $8000 to $BFFF (Window;  Actually Bank determined by PPAGE value.)
Flash Bank $FF - CPU Address range is $C000 to $FFFF (Fixed always)

The PPAGE register is in the CPU Address space at $0030.  Changing the value written here determines the actual 16K Flash bank that is visible to the CPU in the $8000 to $BFFF address range.  This is how the processor can execute code in any Flash bank.  Furthermore, there is an instruction made just for this:  CALL.  With CALL, the programmer can set it up so that the executing code calls a subroutine in another Flash Bank.

Now that you understand how PPAGE works, you are ready for EPAGE and RPAGE.  These function like PPAGE does, but are for EEPROM and RAM, respectively.  Here is a quick summary of the relevant facts for these registers:

EEPROM: DP512 has 4K EEPROM available.  Max possible is 256K with Banks from $00 to $FF.
Global Address Space for 4K EEPROM:  $13F000 - $13FFFF
CPU Logical Address Space Allocated:  $0800 to $0FFF
Pages are 1K in size.  EPAGE Range on DP512 = $FC - $FF
Default Page settings at powerup for CPU Logical Space:
$0800 - $0BFF : EPAGE set to $FE
$0C00 - $0FFF : Bank fixed at $FF

RAM: DP512 has 32K RAM available.  Max possible is 1 megabyte minus 2K for register space, with Banks from $00 to $FF.
Global Address Space for 32K RAM: $0F8000 - $0FFFFF
CPU Logical Address Space Allocated:  $1000 to $3FFF
Pages are 4K in size.  RPAGE Range for DP512 = $F8 - $FF
Default Page settings at powerup for CPU Logical Space:
$1000 - $1FFF : RPAGE set to $FD
$2000 - $2FFF : Bank fixed at $FE
$3000 - $3FFF : Bank fixed at $FF

From this you can see that if the Direct Page register is given a value from $10 to $1F, it can reference that page of 256 bytes on any of the RAM pages mapped to that space by RPAGE.

What about the XGate processor?  It also has a 16 bit address space.  However it does NOT take advantage of any of the paging registers in the S12X.  Instead its memory map is fixed, as follows:

Registers: $0000 - $07FF Logical and Global Spaces
Flash: $0800 - $7FFF Logical = $780800 - $787FFF Global  - Corresponds to PPAGEs $E0 - $E1.
RAM: $8000 - $FFFF Logical = $0F8000 - $0FFFFF Global  - This is the full 32K RAM available.

Last Updated ( Friday, 08 February 2019 18:19 )